Introduction to Digital Logic Gates
Standard commercially available digital logic gates are available in two basic families or forms, TTLwhich stands for Transistor-Transistor Logic such as the 7400 series, and CMOS which stands forComplementary Metal-Oxide-Silicon which is the 4000 series of chips. This notation of TTL or CMOS refers to the logic technology used to manufacture the integrated circuit, (IC) or a “chip” as it is more commonly called.
Generally speaking, TTL logic IC’s use NPN and PNP type Bipolar Junction Transistors while CMOS logic IC’s use complementary MOSFET or JFET type Field Effect Transistors for both their input and output circuitry.
As well as TTL and CMOS technology, simple Digital Logic Gates can also be made by connecting together diodes, transistors and resistors to produce RTL, Resistor-Transistor logic gates, DTL, Diode-Transistor logic gates or ECL, Emitter-Coupled logic gates but these are less common now compared to the popular CMOS family.
Integrated Circuits or IC’s as they are more commonly called, can be grouped together into families according to the number of transistors or “gates” that they contain. For example, a simple AND gate my contain only a few individual transistors, were as a more complex microprocessor may contain many thousands of individual transistor gates. Integrated circuits are categorised according to the number of logic gates or the complexity of the circuits within a single chip with the general classification for the number of individual gates given as:
Classification of Integrated Circuits
Digital Logic States
|Boolean Algebra||Boolean Logic||Voltage State|
|Logic “1”||True (T)||High (H)|
|Logic “0”||False (F)||Low (L)|
TTL Input & Output Voltage Levels
TTL and CMOS Logic Levels
|Device Type||Logic 0||Logic 1|
|TTL||0 to 0.8v||2.0 to 5v (V)|
|CMOS||0 to 1.5v||3.0 to 18v (V)|
Ideal TTL Digital Logic Gate Voltage Levels
Digital Logic Noise
Digital Logic Gate Noise Immunity
Simple Basic Digital Logic Gates
|Diode-Resistor Circuit||Diode-Transistor circuit|
Basic TTL Logic Gates
As the NAND gate contains a single stage inverting NPN transistor circuit (TR2) an output logic level “1” at Q is only present when both the emitters of TR1 are connected to logic level “0” or ground allowing base current to pass through the PN junctions of the emitter and not the collector. The multiple emitters of TR1 are connected as inputs thus producing a NAND gate function.
In standard TTL logic gates, the transistors operate either completely in the “cut off” region, or else completely in the saturated region, Transistor as a Switch type operation.
Emitter-Coupled Digital Logic Gate
The “74” Sub-families of Integrated Circuits
Basic CMOS Digital Logic Gate